On some solid-state imaging devices each provided with a solid-state imaging element group in which a plurality of solid-state imaging elements (unit pixel) to convert an optical signal to an electric signal by photoelectron conversion are arranged in the form of a matrix, such as a CMOS imaging sensor, CCD sensor, near-infrared imaging sensor, or far-infrared imaging sensor, an analog circuit and a digital circuit are mounted on the same chip.
The circuit mounted on the same chip as the solid-state imaging element group includes, for example, a column-parallel A/D converter circuit in which an A/D converter is provided with respect to each column of the solid-state imaging element group, and pixels in one row are read at one time. Since the column-parallel A/D converter circuit can read the data in one row at one time, its reading speed is high as compared with a conventional A/D converter which is not the column-parallel A/D converter, or its reading speed can be at the same level as the conventional A/D converter which is not the column-parallel A/D converter, at a lower operation frequency, so that power consumption can be lowered.
The general column-parallel A/D converter circuit includes, for example, a column-parallel A/D converter circuit (refer to patent document 1, for example) which is composed of a ramp voltage generator circuit to generate a reference voltage (ramp voltage) whose voltage value monotonously increases in a conversion process to convert an analog voltage signal outputted from the solid-state imaging element to digital data, and a counter circuit to output a counted digital value in response to a voltage change of the ramp voltage, and compares the analog voltage signal with a reference voltage signal in synchronization with an counting operation of the counter circuit, and stores a counter value as pixel data when a comparison result is inverted.
A brief description will be made of a configuration of a solid-state imaging device provided with the column-parallel A/D converter disclosed in the patent document 1 with reference to FIG. 10. Here, FIG. 10 partially shows a schematic configuration example of the solid-state imaging device provided with the column-parallel A/D converter circuit disclosed in the patent document 1. In addition, it is assumed that a resolution (defined by the bit number) is 10 bits in the column-parallel A/D converter circuit shown in FIG. 10.
More specifically, as shown in FIG. 10, a solid-state imaging device 1000 disclosed in the patent document 1 is composed of a solid-state imaging element group IPD in which a plurality of solid-state imaging elements PIXij (i=1 to m, j=1 to n) to convert an optical signal to an analog voltage signal Vpix are arranged in the form of a matrix, a vertical decoder VD to select a reading target row in a reading process, a ramp voltage generator circuit 1020 to generate a ramp voltage Vr whose voltage value increases step-by-step according to a counter value of a counter circuit 1040 to be described below in a conversion process to convert the analog voltage signal Vpix to digital data, the counter circuit 1040 to start counting when the voltage value of the ramp voltage Vr starts increasing, a horizontal decoder HD to select a reading target column in the reading process, a converter circuit group 1100 in which converter circuits 1101 to compare the analog voltage signal Vpix with the ramp voltage Vr, and output a signal Vcp′ showing a comparison result are each provided with respect to each column of the solid-state imaging element group IPD, and a digital memory 1050 in which memory circuits 1051 are each provided with respect to each column of the solid-state imaging element group IPD. In addition, the column-parallel A/D converter circuit ADC is composed of the ramp voltage generator circuit 1020, the counter circuit 1040, the converter circuit group 1100, and the digital memory 1050.
The converter circuit 1101 is composed of a capacitative element 1105 having an input end to which the analog electric signal Vpix is inputted through a switch circuit 1102, a capacitative element 1104 having an output end connected to an intermediate node connecting the switch circuit 1102 to the capacitative element 1105 and an input end to which the ramp voltage Vr is inputted through a switch circuit 1103, a voltage comparator circuit 1106 composed of an inverter circuit having an input terminal connected to an output end of the capacitative element 1105 to compare a voltage value of the input terminal with a predetermined threshold voltage value, and a switch circuit 1107 to cause short circuit between an input terminal and an output terminal of the voltage comparator circuit 1106.
Hereinafter, a description will be made of an operation of the column-parallel A/D converter circuit ADC in the solid-state imaging device 1000 with reference to FIGS. 11 and 12.
Here, FIG. 11 shows waveforms of input and output voltage signals and operation states of switch circuits SW1′ to SW3′ in the converter circuit 1101 of the column-parallel A/D converter circuit ADC of the solid-state imaging device 1000 shown in FIG. 10. FIG. 12 shows a relationship among values of the ramp voltage Vr, and analog signal Vpix, and the counter circuit 1040 while the conversion process is executed. In addition, FIG. 12 shows a case where a resolution of the column-parallel A/D converter circuit ADC is 4 bits, the counter circuit 1040 counts 24=16 times in a period Trc, and the voltage value of the ramp voltage Vr increases step-by-step by a unit increase amount in response to the counting operation. In addition, in FIG. 12, SW1′ shows the state of the switch circuit 1102, SW2′ shows the state of the switch circuit 1103, and SW3′ shows the state of the switch circuit 1107.
When an imaging process is started at a time t0, an initialization process is started at a time t1. In the initialization process, a voltage Vrst of the solid-state imaging element PIX at a reset level is sampled.
More specifically, as shown in FIG. 11, a voltage value of the conversion object analog voltage signal Vpix outputted from the solid-state imaging element PIX is equal to the voltage Vrst at the reset level at the time t1, and a voltage value of the ramp voltage Vr is equal to a voltage Vr0 at an initial level. When the initialization process is started at the time t1, the converter circuit 1101 of the column-parallel AJD converter circuit ADC turns on the switch circuit 1102 and the switch circuit 1107, and turns off the switch circuit 1103. Thus, the voltage Vrst of the solid-state imaging element PIXij at the reset level is inputted to the input end of the capacitative element 1105 (C1′), and short circuit is caused between the input terminal and the output terminal of the voltage comparator circuit 1106, and an inversion level Vth of the voltage comparator circuit 1106 is inputted to the output end of the capacitative element 1105 (C1′). Thus, characteristic variation in inversion level of the voltage comparator circuit 1106 is cancelled (auto-zero technique). Then, when the switch circuit 1107 is turned off at a time t2, a difference voltage between the voltage Vrst of the solid-state imaging element PIXij at the reset level and the inversion level Vth of the voltage comparator circuit 1106 is held in the capacitative element 1105 (C1′), and the initialization process is completed.
At a time t3, a sampling process is started for a signal level Vsig of the solid-state imaging element PIXij in an image loading process.
More specifically, at the time t3, the conversion object analog voltage signal Vpix whose voltage value is the voltage Vsig is outputted from the solid-state imaging element PIXij, and inputted to the input end of the capacitative element 1105 (C1′). In addition, at the time t3, the switch circuit 1103 (SW2′) is turned on, and the ramp voltage Vr at the initial level Vr0 is inputted to the input end of the capacitative element 1104 (C2′). At a time t4, the sampling process for the signal level Vsig of the solid-state imaging element PIXij is completed. When the switch circuit 1102 (SW1′) is turned off at the time t4, a difference voltage between the signal level Vsig of the conversion object analog voltage signal Vpix and the initial level Vr0 of the ramp voltage Vr is held in the capacitative element 1104 (C2′).
At a time t5, the conversion process to convert a difference voltage Va to digital data is started, and the ramp voltage Vr increases step-by-step in synchronization with a clock signal CLK, and the counter value of the counter circuit 1040 increases by one in response to the increase of the ramp voltage Vr.
More specifically, as shown in FIG. 12, the voltage value of the difference voltage Va is a value between the voltage value of the ramp voltage Vr corresponding to the counter value “1000” and the voltage value of the ramp voltage Vr corresponding to the counter value “1001”. The counter circuit 1040 sequentially counts up from “0000” by one, and when the counter value changes from “1000” to “1001” at a time t6, a value of the signal Vcp′ outputted from the voltage comparator circuit 1106 is changed (inverted) from H level to L level. When the value of the signal Vcp′ is inverted, the memory circuit 1051 stores the counter value of the counter circuit 1040, that is, “1001” in FIG. 12. Then, the conversion process is completed at a time t7.
The following formula 1 and formula 2 express an input voltage Vin of the voltage comparator circuit 1106 in the column-parallel A/D converter circuit ADC disclosed in the patent document 1 with the inversion level Vth of the comparator circuit 1106, the initial level Vrst of the solid-state imaging element PIXij, the signal level Vsig of the solid-state imaging element PIXij at the time of imaging operation, and the initial level Vr0 of the ramp voltage Yr.Vin=Vr+(Vsig−Vr0)+(Vth−Vrst)  (1)Vin−Vth=Vr−{Vr0+(Vrst−Vsig)}  (2)
Therefore, based on the formula 1, the formula 2, and FIG. 11, the ramp voltage Vr at the time of the output change of the voltage comparator circuit 1106, that is, when Vin-Vth=0 is expressed by the following formula 3.Vr=Vr0+(Vrst−Vsig)=Vr0+Va (provided that Vin−Vth=0)  (3)
In addition, in the case of the column-parallel A/D converter circuit ADC disclosed in the patent document 1, the conversion process to convert the conversion object analog voltage signal Vpix to digital data D [(z−1):0] (z is the bit number of the digital data) requires a time for 2z steps, that is, for the 2z clocks because one step corresponds to one clock in general. More specifically, when the bit number z=10 in the digital data, a time for 210=1024 clocks is required.
By the way, recently, the solid-state imaging device provided with the column-parallel A/D converter circuit is required to be higher in resolution and higher in resolution accuracy, so that various techniques are proposed to shorten a process time of the column-parallel A/D converter circuit.
The technique to shorten the process time of the column-parallel A/D converter circuit includes a sub-ranging method in which the digital data is divided to upper-order bits and lower-order bits, and the digital data is provided by a two-step conversion process composed of a first conversion process to convert the conversion object analog voltage signal to the digital data with a upper-order bit converting resolution based on the bit number of the upper-order bits, and a second conversion process to convert a difference voltage value between a voltage value corresponding to the conversion result of the first conversion process and a voltage value of the conversion object analog voltage signal, to the digital data with a lower-order bit converting resolution based on the bit number of the lower-order bits.
Hereinafter, a description will be made of a concept of a general operation of a conventional sub-ranging A/D converter circuit with reference to FIGS. 8 and 9. Here, FIG. 8 shows a relationship among a conversion object analog voltage signal Vpix, a voltage value corresponding to the upper-order bits found in the first conversion process, a difference voltage Vdif, and a voltage value corresponding to the digital data, in the general sub-ranging A/D converter circuit. FIG. 9 shows configurations of a first ramp voltage Vrc used in the first conversion process and a second ramp voltage Vrf used in the second conversion process. In addition, in FIGS. 8 and 9, it is assumed that the digital data is composed of 4 bits, and the first conversion process to find the upper-order 2 bits and the second conversion process to find the lower-order 2 bits are executed to simplify the description. In addition, a voltage Ver shown in FIG. 8 represents a quantizing error at the time of the A/D conversion process.
As shown in FIGS. 8 and 9, in order to find the upper-order 2 bits, the first conversion process uses the ramp voltage Vrc which monotonously increases by a first change amount Δ1 provided by dividing a voltage width Vfs of the conversion object analog voltage signal Vpix by split number 4 based on the resolution of 2 bits. In FIGS. 8 and 9, the conversion object analog voltage signal Vpix is provided between digital values “01” and “10” of the counter circuit, so that when the digital value of the counter circuit (corresponding to the counter circuit 1040 in FIG. 10) shifts to “10”, an output value of the voltage comparator circuit (corresponding to the voltage comparator circuit 1106 in FIG. 10) is inverted. The counter value “10” at this time is the value of the upper-order bits, and the difference voltage value Vdif at this time is held as a process target of the second conversion process.
As shown in FIGS. 8 and 9, in order to find the lower-order 2 bits, the second conversion process uses the ramp voltage Vrf which monotonously decreases by a second change amount ΔV2 provided by dividing the first change amount ΔV1 by split number 4 based on the resolution of 2 bits. In FIGS. 8 and 9, the difference voltage value Vdif is provided between the digital values “10” and “01”, and when the counter value shifts to “01” in the counter circuit, the output value of the voltage comparator circuit is inverted. The counter value “01” at this time is the value of the lower-order bits, whereby it is found that digital data D [(z−1):0]=“1001”.
The sub-ranging column-parallel A/D converter circuit includes, for an example, a column-parallel A/D converter circuit internally containing a difference detection circuit (refer to a patent document 2, for example), as shown in FIG. 13, which is provided with a conversion circuit 2000 having a sampling and holding circuit (hereinafter, simply referred to as the “S/H circuit” occasionally) 2001 to hold the conversion object analog voltage signal Vpix, a comparator 2002 to compare the conversion object analog voltage signal Vpix with the ramp voltage Yr (=upper-order bit converting ramp voltage Vrc), a difference detection circuit 2004 to output difference voltage value between the conversion object analog voltage signal Vpix and the ramp voltage Vrc, a S/H circuit 2005 to hold the voltage value outputted from the difference detection circuit 2004, a logic circuit 2003 having a function to control and make the S/H circuit 2005 hold the difference voltage value at the time of the output change of the comparator 2002, an attenuation circuit 2006 to generate the ramp voltage Vrf in which a voltage width of the ramp voltage Vrc is adjusted to 1/K, a comparator 2007 to compare the ramp voltage Vrf with the voltage held in the S/H circuit 2005, and a logic circuit 2008 to generate a signal Vcp_1′ to define a timing for holding the value of the counter circuit corresponding to the value of the upper-order bits, based on the output signal of the comparator 2007.
In addition, in the case of the column-parallel A/D converter circuit disclosed in the patent document 2, when it is assumed that the bit number of the digital data is 10, the bit number of the upper-order bits is 5, and the bit number of the lower-order bits is 5, a time for 25=32 clocks is required for the first conversion process, and a time for 25=32 clocks is required for the second conversion process, so that a time for 64 (=32+32) clocks is required. Therefore, as described above, while column-parallel A/D converter circuit disclosed in the patent document 1 to convert the conversion object analog voltage signal to the digital data by the one-step conversion process needs the time for 1024 clocks, the sub-ranging column-parallel A/D converter circuit disclosed in the patent document 2 only needs the time for 64 clocks in the conversion process, so that the process time is considerably shortened.
As another sub-ranging column-parallel A/D converter circuit, there is a column-parallel A/D converter circuit using a capacity ratio (refer to a patent document 3, for example), as shown in FIG. 14, composed of a S/H circuit 3001 to hold the conversion object analog voltage signal Vpix, a comparator circuit 3005 to compare the conversion object analog voltage signal Vpix with a reference voltage, a switch circuit 3002 to input the ramp voltage Vrc to the comparator circuit 3005 at the time of the execution of the first conversion process to find the upper-order bits of the converted digital data, a capacitative element 3003 to input the ramp voltage Vrf to the comparator circuit 3005 as a reference voltage at the time of the execution of the second conversion process to find the unconverted bits after the first conversion process, a capacitative element 3004 and the capacitative element 3003 to hold the voltage value of the reference voltage at the time of the output change of the comparator circuit 3005 in the first conversion process, and a logic circuit 3006 to generate a control signal to hold the ramp voltage Vrc in the capacitative element 3004 at the time of the output change of the comparator circuit 3005 in the first conversion process.
According to the column-parallel A/D converter circuit disclosed in the patent document 3, in the first conversion process, the conversion object analog voltage signal Vpix is inputted to the comparator circuit 3005 through the S/H circuit 3001, and the switch circuit 3002 is turned on and the ramp voltage Vrc is inputted. In addition, a configuration of the ramp voltage Vrc is the same as that of the ramp voltage Vrc shown in FIGS. 8 and 9. When the output of the comparator circuit 3005 is inverted while the ramp voltage Vrc monotonously increases step-by-step, the switch circuit 3002 is turned off by the control signal from the logic circuit 3006, and the ramp voltage Vrc is held in the capacitative element 3004. At this time, the digital value of the counter circuit is stored in a memory circuit (not shown) as the value of the upper-order bits of the digital data. In the second conversion process, the ramp voltage Vrf monotonously decreasing step-by-step is inputted. When the output of the comparator circuit 3005 is inverted, the digital value of the counter circuit is stored in the memory circuit (not shown) as the value of the lower-order bits of the digital data. In addition, a configuration of the voltage Vrf is the same as that of the ramp voltage Vrf shown in FIGS. 8 and 9.
As shown in FIG. 14, since the column-parallel A/D converter circuit disclosed in the patent document 3 is composed of the one S/H circuit, the two capacitative elements, and the switch circuit, its circuit size can be small.
As still another sub-ranging column-parallel A/D converter circuit, there is a column-parallel A/D converter circuit internally containing an integration circuit (refer to a patent document 4, for example), as shown in FIG. 15, which is composed of an input circuit 4010 to receive the conversion object analog voltage signal Vpix and reference voltages VDE1 and VDE2, an integration circuit 4020 to integrate the reference voltage VDE 1 outputted from the input circuit 4010 at the time of a first conversion process, and the reference voltage VDE2 outputted from the input circuit 4010 at the time of a second conversion process, a comparator circuit 4030 to compare an output voltage of the integration circuit 4020 with a reference voltage Vref, and a logic circuit 4040 to generate a control signal used to hold the voltage level of the integration circuit 4020 at the time of output change of the comparator circuit 4030 in the first conversion process. In addition, FIG. 16 shows a variation of the column-parallel A/D converter circuit internally containing the integration circuit disclosed in the patent document 4, and its operation principle is the same as that of the column-parallel A/D converter circuit internally containing the integration circuit shown in FIG. 15.
According to the column-parallel A/D converter circuit disclosed in the patent document 4, the integration circuit 4020 integrates the reference voltage VDE1 (corresponding to the first change amount ΔV1 in the patent document 2 and the patent document 3) and the reference voltage VDE2 (corresponding to the second change amount ΔV2 in the patent document 2 and the patent document 3) to generate the voltage corresponding to the upper-order bits and the voltage corresponding to the lower-order bits to be compared with the conversion object analog voltage signal Vpix, without using the monotonously increasing ramp voltage Vrc and the monotonously decreasing ramp voltage Vrf unlike in the patent document 2 and the patent document 3.
According to the column-parallel A/D converter circuit disclosed in the patent document 4, before the execution of the first conversion process, the switch circuit 4012 is turned on and the switch circuit 4014 is turned off and then the conversion object analog voltage signal Vpix is inputted to the integration circuit 4020. In the first conversion process, the switch circuit 4012 is turned off and the switch circuit 4013 is connected to the side of the reference voltage VDE1 and then the switch circuit 4014 is turned on, and then the reference voltage VDE1 (corresponding to the first ramp voltage Vrc having a relatively large inclination) is integrated. When the output value of the comparator circuit 4030 is inverted, the digital value of the counter circuit (not shown) at this time is stored as the value of the upper-order bits, and the switch circuit 4014 is turned off by the control signal outputted from the logic circuit 4040. Thus, the difference voltage value Vdif is held in the integration circuit 4020. In the second conversion process, the switch circuit 4013 is connected to the side of the reference voltage VDE2 and then the switch circuit 4014 is turned on, and then the reference voltage VDE2 (corresponding to the second ramp voltage Vrf having an inclination smaller than that of the first ramp voltage Vrc) is integrated. When the output value of the comparator circuit 4030 is inverted, the digital value of the counter circuit (not shown) at this time is stored as the value of the lower-order bits, and the second conversion process is completed.
As described above, since the conversion object analog voltage signal is converted to the digital data by the two conversion processes in the sub-ranging column-parallel A/D converter circuit disclosed in the patent documents 2 to 4, the number of steps for the conversion process can be considerably reduced, so that the time required for the conversion process can be shortened.    Patent document 1 Japanese Unexamined Patent Publication No. 2000-286706    Patent document 2 Japanese Unexamined Patent Publication No. 1999-168383    Patent document 3 Japanese Unexamined Patent Publication No. 2002-232291    Patent document 4 Japanese Unexamined Patent Publication No. 2005-348325